module op_exp0(a,b,c,d,e,f,g,q);
input a,b,c,d,e,f,g;
output q;
wire sum1,sum2,sum3,sum4;
assign sum1 = a + b + c;
assign sum2 = a + b;
assign sum3 = a + b + e;
assign sum4 = a + b + f;
assign q = sum1 & sum2 & ~(sum3 | sum4);
endmodule
